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| | Thursday, June 13, 2002, 10:30 AM - 12:00 PM | Room: 288
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SESSION 44
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| | Test Cost Reduction for SoCs
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| | Chair: Yervant Zorian - Logic Vision, San Jose, CA
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| | Organizers: Seiji Kajihara, Kwang Ting (Tim) Cheng
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| | The papers in this session focus on test cost reduction for SoC designs. The proposed test compression and scheduling methods bring siginifcant reduction of test application time, test data volume and/or power dissipation during testing. The first paper describes a method of encoding test data. The second paper presents control schemes for testing embedded cores. The last paper describes an integrated framework for SOC test automation.
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| |  44.1 |
Reduction of SOC Test Data Volume, Scan Power and Testing Time Using Alternating Run-length Codes
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| | | Speaker(s): | Anshuman Chandra - Duke Univ., Durham, NC
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| | | Author(s): | Anshuman Chandra - Duke Univ., Durham, NC
Krishnendu Chakrabarty - Duke Univ., Durham, NC
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| | 44.2 |
Embedded Test Control Schemes for Compression in SoCs |
| | Speaker(s): | Douglas Kay - Cisco Systems, Inc., San Jose, CA
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| | Author(s): | Douglas Kay - Cisco Systems, Inc., San Jose, CA
Sung Chung - Cisco Systems, Inc., San Jose, CA
Samiha Mourad - Santa Clara Univ., Santa Clara, CA
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| | 44.3 |
Integrated Wrapper/TAM Co-Optimization, Constraint-Driven Test Scheduling, and Tester Data Volume Reduction for SOCs |
| | Speaker(s): | Vikram Iyengar - Duke Univ., Durham, NC
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| | Author(s): | Vikram Iyengar - Duke Univ., Durham, NC
Krishnendu Chakrabarty - Duke Univ., Durham, NC
Erik Jan Marinissen - Philips Research Labs., Eindhoven, The Netherlands
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